Characteristics of various packaging forms and specifications of integrated circuits
Characteristics of various packaging forms and specifications of integrated circuits
Integrated circuit, abbreviated as IC; some commonly used electronic components (such as resistors, capacitors, transistors, etc.) and the connections between these components are integrated with specific functions through semiconductor technology circuits. What are the characteristics of various packaging forms of integrated circuits? If you are interested in what this article is about to cover, keep reading.
The seven common packaging forms of integrated circuits are as follows:
1. SO package
Small-scale integrated circuits with fewer leads are mostly used in this small package. SO packages are divided into several types. The chip width is less than 0.15in and the number of electrode pins is relatively small (between 8 and 40 pins), which is called SOP package; the chip width is more than 0.25in and the number of electrode pins is more than 44. , called SOL package, this chip is commonly used in random access memory (RAM); the chip width is more than 0.6in, the number of electrode pins is more than 44, called SOW package, this chip is commonly used in programmable memory (E2PROM). Some SOP packages come in miniaturized or thin packages, called SSOP packages and TSOP packages, respectively. Most SO packages have pins with wing electrodes, and some memories use J-shaped electrodes (called SOJs), which are useful for expanding storage capacity on the socket. The pin pitch of SO package is 1.27mm, 1.0mm, 0.8mm, 0.65mm and 0.5mm.
2. QFP package
QFP (Quad Flat Package) is a four-side pin flat package, which is one of the main packaging forms of surface-mounted integrated circuits. The pins are drawn out from four sides in a wing (L) shape. There are three kinds of substrates: ceramic, metal and plastic. In terms of quantity, plastic packaging accounts for the vast majority. When the material is not specifically indicated, it is mostly plastic QFP. Plastic QFP is the most popular multi-pin LSI package, which is not only used in digital logic LSI circuits such as microprocessors and gate arrays, but also in analog LSI circuits such as VTR signal processing and audio signal processing. The pin center distance has various specifications such as 1.0mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm, 0.3mm, etc. The minimum limit of the pin spacing is 0.3mm, and the maximum is 1.27mm. The maximum number of pins in the 0.65mm center distance specification is 304.
To prevent pin deformation, several improved QFP varieties have appeared. For example, a BQFP with resin buffers at the four corners of the package, it is provided with protrusions at the four corners of the package body to prevent the pins from being bent and deformed during transportation or operation.
3. PLCC package
PLCC is a leaded plastic chip carrier package for integrated circuits. Its pins are hooked back inward, called hook-shaped (J-shaped) electrodes. The number of electrode pins is 16~84, and the distance is 1.27mm. PLCC packaged integrated circuits are mostly programmable memories. The chip can be installed on a special socket and can be easily removed to rewrite the data in it; in order to reduce the cost of the socket, the PLCC chip can also be directly soldered on the circuit board, but it is difficult to solder by hand. The PLCC has two shapes: square and rectangular. The square one is called JEDEC MO-047, with 20 to 124 pins; the rectangular one is called JEDEC MO--052, with 18 to 32 pins.
4. LCCC package
LCCC is a package without pins in the SMD integrated circuit packaged by the ceramic chip carrier; the chip is packaged on the ceramic carrier, with square and rectangular shapes, and the leadless electrode terminals are arranged on the four sides of the bottom surface of the package. The number of squares is 16, 20, 24, 28, 44, 52, 68, 84, 100, 124 and 156, and the rectangles are 18, 22, 28 and 32. There are two types of pin pitch, 1.0mm and 1.27mm.
The characteristic of the LCCC lead-out terminal is that there is a castle-like metallized groove on the side of the ceramic shell, which is connected to the gold-plated electrode on the bottom surface of the shell, which provides a short signal path, low inductance and capacitance loss, and can be used in high-frequency working conditions, such as microelectronics. Processor unit, gate array and memory.
The chips of LCCC integrated circuits are fully sealed, with high reliability, but high price. They are mainly used in military products, and the issue of whether the thermal expansion coefficient between the device and the circuit board is consistent must be considered.
5. PQFN package
The PQFN is a leadless package, square or rectangular, with a large exposed pad at the center of the bottom of the package for improved thermal performance. There are conductive pads that make electrical connections around the perimeter of the package around the large pads. Since the PQFN package does not have wing-shaped pins like SOP, QFP, etc., the conductive path between the internal pins and the pad is short, the self-inductance coefficient and the wiring resistance in the package are very low, so it can provide good electrical performance. Due to its good electrical and thermal properties, small size and low mass, PQFN has become an ideal choice for many new applications. PQFN is ideal for high-density applications such as cell phones, digital cameras, PDAs, DVs, smart cards, and other portable electronic devices.
6. BGA package
BGA package is ball grid array package. It changes the J-shaped or wing-shaped electrode pins of the original device PccQFP package into ball pins, and changes the electrodes drawn out from the "single linear" sequence around the device body into "full" under the bottom surface of the body. Flat" grid array arrangement. In this way, the pin spacing can be evacuated and the number of pins can be increased. The solder ball array can be fully or partially distributed on the bottom surface of the device.
From the point of view of assembly and welding, the mounting tolerance of BGA chips is 0.3mm, which is much lower than the mounting accuracy of QFP chips of 0.08mm. This significantly improves the placement reliability of BGA chips, and greatly reduces the process error rate. The assembly requirements can be basically met with ordinary multi-function placement machines and reflow soldering equipment.
The use of BGA chips shortens the average line length of the product and improves the frequency response and other electrical properties of the circuit.
When soldering with reflow equipment, the high surface tension of the solder balls results in a self-alignment effect (also called "self-centering" or "self-positioning" effect) of the chip, which improves the quality of assembly soldering.
Because of the obvious advantages of BGA packaging, the BGA varieties of large-scale integrated circuits are also rapidly diversifying. Now there are many forms, such as ceramic BGA (CBGA), plastic BGA (PBGA) and micro BGA (Micro-BGA, µBGA or CSP), etc. The main difference between the first two is the base material of the package, such as CBGA using ceramic, PBGA uses BT resin; the latter refers to those miniature integrated circuits whose package size is relatively close to the chip size.
The general BGA chips that can be seen at present have three kinds of ball pitches: 1.5mm, 1.27mm and 1.0mm; while the ball pitches of µBGA chips are 0.8mm, 0.65mm, 0.5mm, 0.4mm and 0.3mm.
7. CSP package
The full name of CSP is Chip Scale Package, which means chip scale package. It is the product of further miniaturization of BGA, and the size of the package can be as big as the size of the bare chip. That is, the side length of the packaged IC size is not greater than 1.2 times the chip length, and the IC area is only 1.4 times larger than the die (Die). CSP packaging can make the ratio of chip area to package area exceed 1:1.14, which is very close to the ideal situation of 1:1.
Under the same chip area, the number of pins that CSP can achieve is obviously much more than that of TSOP and BGA. TSOP is up to 304 pins, BGA pin limit can reach 600, and CSP can theoretically reach 1000. Due to such a highly integrated feature, the distance from the chip to the pin is greatly shortened, the impedance of the line is significantly reduced, and the attenuation and interference of the signal are greatly reduced. The CSP package is also very thin, and the most effective heat dissipation path from the metal substrate to the heat sink is only 0.2mm, which improves the heat dissipation capability of the chip.
The current CSP is also mainly used in the packaging of integrated circuits with fewer I/O terminals, such as computer memory sticks and portable electronic products. In the future, it will be widely used in information appliances (IA), digital television (DTV), e-book (E-Book) wireless network WLAN/GigabitEthernet, ADSL and other emerging products.
